HV610 features hvcmos ? technology operating output voltage up to +50/-40v shift register speed 40mhz @ v dd = 5v data speed up to 160mhz @ v dd = 5v 32 high voltage outputs cmos/ttl compatible applications high speed print head driver lcd driver ? ? ? ? ? ? ? ? 32-channel serial to parallel converter with high voltage push-pull outputs typical application diagram general description the HV610 is a 32-channel high voltage, medium current driver ic. the outputs can be either at v pps , v nn , hiz, or hvgnd. data is shifted through four parallel 8-bit shift registers on the low to high transition of the clock. a data output buffer is provided for cascading devices. data is transferred to a 32-bit latch when logic level high is applied to the le input. the clr signal will reset both the shift register and the latch. output states are controlled by pos, and neg input signals, and by data in the latch. all outputs are tri-stated upon a logic high on the hiz input signal. HV610 lcd or piezo array level translators decoder logic 32 hv buffers 32-bit latch four 8-bit shift registers clk clr le pos neg hiz d in (1-4) d out (1-4) hv out 1 hv out 32 gnd v dd 5v v pps v pplt hvgnd v nn 50v 50v -40v host controller
2 HV610 ordering information device 64-lead tqfp 10x10x1.20mm body, 0.50mm pitch HV610 HV610fg-g absolute maximum ratings parameter value supply voltage, v dd -0.5v to 6v supply voltage, v pp 55v supply voltage, v nn -45v logic input levels -0.5v to v dd +0.5v operating junction temperature range -40c to +125c storage temperature range -65c +150c all voltages referenced to gnd. operating supply voltages and temperatures (all voltages referenced to gnd) symbol parameter min typ max units conditions v dd logic supply voltage 4.5 5.0 5.5 v --- v pps positive high voltage supply for hv output source 25 - 50 v for f out = 200khz v pplt positive high voltage supply for level translators 47.5 - 50 v --- v nn negative high voltage supply -15 - -40 v for f out = 200khz hvgnd high voltage ground -5 - +5 v --- v ih high-level input voltage 2.0 - v dd v --- v il low-level input voltage 0 0.8 v --- t a operating ambient temperature -40 - +85 c --- -g indicates package is rohs compliant (green) pin con? guration 1 64-lead tqfp (top view) 64 product marking yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = green packaging *may be part of top marking top marking bottom marking yyww HV610fg lllllllll cccccccc aaa
3 HV610 symbol parameter min typ max units conditions dc electrical characteristics over operating supply voltages and temperature, unless otherwise noted. i dd v dd supply current - - 15 ma f clk = 40mhz i ddq v dd quiescent supply current - - 0.1 ma all logic inputs = v dd or 0v - - 2.2 per each input at ttl level i pps v pps supply current - - 412 ma cl = 700pf, f out = 200khz, all channels switching per hv out waveform i ppsq v pps quiescent supply current - - 100 a v pps = 50v, outputs static, v pplt = 50v i pplt v pplt supply current - - 17 ma f out = 200khz i ppltq v ppltq quiescent supply current - - 100 a v pps = 50v, outputs static, v pplt = 50v i nn v nn supply current - - 433 ma cl = 700pf, f out = 200khz, all channels switching per hv out waveform i nnq v nn quiescent supply current - - 100 a v nn = -40v, outputs static i ih logic input high current - - 50 a v ih = v dd - - 50 a v ih = 2.0v i il logic input low current - - -50 a v il = 0v - - -50 v il = 0.8v i ol d out low level logic sink current - - 12 ma d out < 0.8v i oh d out high level logic source current - - -12 ma d out > 2.0v v oh high level output hv out v pps -10 - - v ihv out = -35ma, v pps = +50v, v pplt = +50v, v nn = -40v d out v dd -1.0 - - id out = -15ma v ol low level output hv out --v nn +10 v ihv out = 35ma, v pps = +50v, v pplt = +50v, v nn = -40v d out - - 1.0 id out = 15ma v omid mid level output -10 - 10 v i mid = 35ma, v pps = +50v, v pplt = +50v, v nn = -40v c din lv input capacitance - - 10 pf --- ac electrical characteristics over operating supply voltages and temperature, unless otherwise noted. symbol parameter min typ max units conditions f clk clock frequency 0-40 mhz 0 tov dd clock input 0 - 33 0 to 2.0v clock input f out output switching frequency switching waveform - - 200 khz cl = 700pf, 5% to 95% v pplt = 50v t c clock high/low pulse width 10 - - ns 0 - v dd logic signals 10 - - 0 - 2.0v logic signals
4 HV610 ac electrical characteristics (cont.) over operating supply voltages and temperature, unless otherwise noted. symbol parameter min typ max units conditions t sud data setup time before clock rises 12.5 - - ns 0 - v dd logic signals 15 - - 0 - 2v logic signals t hd data hold time after clock rises 2 - - ns --- t suc le from clk setup time 15 - - ns --- t le le pulse width 10 - - ns --- t woc width of clr, pos, neg, hiz pulses 500 - - ns --- t dhiz hiz input to hv out hiz state delay - - 400 ns --- t clrh clr input to hv out delay - - 1.1 s --- t dclr clr input to d out delay 5 - 50 ns --- t dd clock positive edge to d out delay 2.5 - 12.5 ns c ldout = 30pf t phv delay time from inputs for hv out to start rise/fall - - 500 ns v pplt = 50v t hiz output hiz state before each transi- tion - - 100 ns v pplt = 50v t hr time for output to go from 95% of v pps /v nn to 99% of v pps /v nn - - 0.5 s c l = 700pf, hv gnd to v pps , or hv gnd to v nn transitions - - 1.0 s c l = 700pf, v pps to v nn , or v nn to v pps transitions t hg time for output to go from hv gnd 1v to within 1% of hv gnd - - 0.5 s cl = 700pf, v nn to hv gnd , or v pps to hv gnd transitions t rpn , t fpn output rise/fall time (per function table3) - - 1.6 s cl = 700pf, v pplt = 50v, transi- tions between v pps and v nn t rr , t fr output rise/fall time from hv gnd to 95% of v pps /v nn - - 0.9 s cl = 700pf, v pplt = 50v t rg , t fg output rise/fall time from 95% of v pps /v nn to hv gnd 1v - - 0.9 s cl = 700pf, v pplt = 50v t orpn , t ofpn delay time from input edges to 95% of hv out rise/fall (per function table 3) - - 1.8 s cl = 700pf, v pplt = 50v, transi- tions between v pps and v nn t org , t ofg delay time from input edges to 95% of hv out rise/fall from hv gnd to v pps or v nn , or from v pps /v nn to within 1v of hv gnd - - 1.1 s cl = 700pf, v pplt = 50v, transitions between v pps /v nn and hv gnd ja thermal resistance, junction to ambient -59- o c/w mounted on 4-layer pcb board
5 HV610 function table 1 (s/r and d out of s/r one of four) inputs outputs data (n-1) clk clr le, pos, neg, hiz s/r1...8(n)* data out l or h l to h l x s/r1 = d in (n-1) s/r2 = s/r1(n-1) . . s/r8 = s/r7(n-1) s/r8(n-1) x l l x s/r1..8(n-1) d out (n-1) x h l x s/r1..8(n-1) d out (n-1) xxh x l l notes: h = high level, l = low level, x = irrelevant, *d in 1 to d in 4 => 1 st s/r1..8 to 4 th s/r1..8, *1 st s/r1..8 to 4 th s/r1..8 = d1..d8, d9..d16, d17..d24, d25..d32 function table 2 (latch) inputs outputs d1..32 le clr clk, pos, neg, hiz ld1..32 xxhxl l or h h l x l or h x l l x unchanged function table 3 (hv outputs) inputs outputs pos neg hiz clk le clr d in ld1..32 hv out 1..32 xxhxxxxx hiz hh lx l lxh hiz lllxllxx hvgnd x x l x l l x l hvgnd lhlxl lxh v nn hllxllxh v pps x x l x x h x x hvgnd
6 HV610 functional block diagram hvgnd hv out 32 v nn v pps hvgnd hv out 1 v nn v pps d1 d8 d9 d16 d17 d24 d25 d32 ld1 ld32 v dd clr le d in 1 d in 2 d out 1 d in 3 d out 3 clk d out 2 d in 4 d out 4 pos neg hiz v nn v pplt v nn vpplt 8 bit shift register 32 bit latch decoder level xlator 8 bit shift register 8 bit shift register 8 bit shift register decoder level xlator level xlator level xlator level xlator level xlator input and output equivalent circuits v dd input dgnd logic inputs dgnd data out logic data output high voltage outputs v dd hvgnd hv out v nn v pps
7 HV610 switching waveforms data vali d 50% 50% t suc t le t sud t hd t c t dd t dclr t clrh d in clk clr le d out v ih v il v ih v il v ih v il v ih v il t phv 95% 5% 5% 5% 95% t phv t phv t fpn t rg t rr t org t org t ofpn 50% 50% 50% t woc 95% 5% 5% 5% 95% t rpn t fr t orpn t ofg t ofg t fg hvgnd - 1v hvgnd + 1v 50% 50% 50% t hr t hr t hr t hr t hg t hg t phv t phv t phv t clrh clk clr pos neg hv out hv out v ih v il v ih v il v ih v il v pps hvgnd v nn v pps hvgnd v nn v nn v pps hvgnd t dhiz v ih v il hv out hiz
8 HV610 tqfp pin description 1v nn 2hv out 23 3hv out 22 4hv out 21 5hv out 20 6hv out 19 7hv out 18 8hv out 17 9hv out 16 10 hv out 15 11 hv out 14 12 hv out 13 13 hv out 12 14 hv out 11 15 hv out 10 16 v nn 17 hvgnd 18 v pps 19 hv out 9 20 hv out 8 21 hv out 7 22 hv out 6 23 hv out 5 24 hv out 4 25 hv out 3 26 hv out 2 27 hv out 1 28 v nn 29 v pps 30 hvgnd 31 v pplt 32 d in 1 33 d in 2 34 d in 3 35 d in 4 36 dgnd 37 pos 38 neg 39 hiz 40 clk 41 clr 42 le 43 v dd 44 dgnd 45 nc 46 d out 4 47 d out 3 48 d out 2 49 d out 1 50 v pplt 51 hvgnd 52 v pps 53 v nn 54 hv out 32 55 hv out 31 56 hv out 30 57 hv out 29 58 hv out 28 59 hv out 27 60 hv out 26 61 hv out 25 62 hv out 24 63 v pps 64 hvgnd pin # function pin # function pin # function pin # function power-up / power-down sequence step description 1 connect dgnd and hvgnd 2 apply v dd 3 set all inputs (data, clk, le, pos, neg, hiz, etc.) to a known state 4 apply v nn 5 apply v pplt 6 apply v pps power-down sequence should be the reverse of the above. to insure the safest power-up/down sequence, the intervals between power-up signals should be between 1msec to 10msec, after the previous signal changed 95% of its ? nal level.
9 HV610 (the package drawings in this data sheet may not re? ect the most current speci? cations. for the latest package outline information go to http://www.supertex.com/packaging.html .) seating plane gauge plane l l1 l2 view b view b seating plane top view d d1 e e1 b e side view a2 a a1 note 1 (index area d1/4 x e1/4) 1 64 doc.# dsfp-HV610 nr061107 symbol a a1 a2 b d d1 e e1 e l l1 l2 dimension (mm) min 1.00 0.05 0.95 0.17 11.80 9.80 11.80 9.80 0.50 bsc 0.45 1.00 ref 0.25 bsc 0 o nom - - 1.00 0.22 12.00 10.00 12.00 10.00 0.60 3.5 o max 1.20 0.15 1.05 0.27 12.20 10.20 12.20 10.20 0.75 7 o jedec registration ms-026, variation acd, issue d, jan. 2001. drawings not to scale. note 1: a pin 1 identi? er must be located in the index area indicated. the pin 1 identi? er may be either a mold, or an embedded metal or marked feature. 64-lead tqfp package outline (fg) 10x10mm body, 1.2mm height (max.), 0.50mm pitch
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